This invention is in the field of semiconductor power devices. Disclosed embodiments are directed to the surface structure of vertical power transistors.
As known in the art, semiconductor power switching devices are ideally capable of conducting large currents with minimal voltage drop when in the on-state while blocking large reverse voltages with minimal current conduction when in the off-state, with minimal switching times and minimal switching power consumption. Improvements in manufacturing yield and reduction in manufacturing cost are also sought. Advances toward these ideal attributes have largely been made in modern power transistors through innovations in device architecture, rather than through shrinking of device features sizes as in the case of low-power semiconductor devices such as digital logic and memory devices.
Vertical power devices are now widely used in many power applications. These devices are vertical in the sense that current is conducted vertically through a drift region between the device surface and its substrate. The length of this drift region can absorb a large depletion region in the off-state and thus establish a high reverse breakdown voltage, which enables high voltage operation. Well-known types of vertical power devices include vertical drift metal-oxide-semiconductor (VDMOS) field-effect transistors, insulated gate bipolar transistors (IGBTs), and gated power diodes, all of which include a drift region sufficient to support the desired high breakdown voltage. VDMOS devices have become particularly attractive because of their fast switching speeds, and as such are particularly well-suited for implementation into switched-mode power supplies.
FIG. 1a illustrates, in cross-section, an example of the construction of a conventional n-channel vertical drift MOS transistor. VDMOS 2 of FIG. 1a has a drain terminal at n+ substrate 4, and a drift region provided by n-type epitaxial layer 6, which overlies substrate 4 and extends to the surface of the device as shown. P-type body regions 8 at the surface of n-type epitaxial layer 6 serve as the VDMOS body region, within which one or more n+ regions 10 serve as the source of VDMOS 2. Gate dielectric 11 and gate electrode 12 overlie portions of p-type body regions 8 between source region 10 and the drain at n-type epitaxial layer 6. Bias is supplied to n+ source regions 10 and p-type body regions 8 (typically at p+ contact regions, not shown), so that the body node of VDMOS 2 is biased at the source potential. Other conductors (not shown) contact gate electrode 12 and substrate 4 to provide gate and drain bias, respectively. As in any n-channel MOS transistor, vertical power VDMOS 2 is biased into the on-state by a voltage at gate electrode 12 that exceeds the transistor threshold voltage, in combination with a sufficient drain-to-source bias. The drain-to-source bias in typical power applications is typically very high (e.g., as high as from several hundred to over one thousand volts). As shown in FIG. 1a, on-state source-drain current Ids conducts from source regions 10 laterally along an inversion layer in the body region of p-type body regions 8, and vertically through epitaxial layer 6 into substrate 4 at the transistor drain. The on-resistance of VDMOS 2 includes the channel resistance Rch in p-type body regions 8, but is typically dominated by the resistance Repi of n-type epitaxial layer 6 because of the thickness and relatively light dopant concentration of that layer. While an increase in the doping concentration of epitaxial layer 6 would reduce resistance Repi and thus reduce the overall on-resistance of VDMOS 2, the breakdown voltage of VDMOS 2 is directly related to the thickness of its n-type epitaxial layer 6 (i.e., the VDMOS “drift” length), and is inversely related to the dopant concentration of the more lightly-doped epitaxial layer 6. Because typical VDMOS devices must withstand high drain-to-source voltages (e.g., on the order of hundreds of volts) in the off-state, a tradeoff between on-resistance and off-state breakdown voltage is required.
Also as known in the art, “superjunction” VDMOS transistors address this tradeoff. FIG. 1b illustrates an example of such a conventional superjunction VDMOS 2′, also for the case of an n-channel device. Superjunction VDMOS 2′ is constructed similarly as non-superjunction VDMOS 2 of FIG. 1a insofar as the surface structures (p-type body regions 8, n+ source regions 10, gate electrode 12, etc.) are concerned. However, in contrast to the non-superjunction VDMOS 2 of FIG. 1a, the epitaxial region of superjunction VDMOS 2′ is filled with p-type doped “pillars” 9 formed into epitaxial layer 6′. These p-type pillars 9 may be constructed by ion implantation during the formation of epitaxial layer 6′ silicon, for example in a multiple step epitaxial process in which a p-type pillar implant is performed after epitaxy of a portion of layer 6′, such that each pillar 9 is formed as a number of vertically aligned segments. P-type body regions 8 and n+ source regions 10 are typically self-aligned with gate electrode 12, with p-type body regions 8 typically implanted prior to the n+ source implant, and receiving a dedicated drive-in anneal, so as to extend farther under gate electrode 12 than its corresponding n+ source region 10, with p-type body regions 8 typically extending slightly into the surface region of the n-type epitaxial region. The dopant concentration of p-type body regions 8 is optimized for the desired MOSFET characteristics, such as threshold voltage and punch-through, while the dopant concentration of p-type pillars 9 is optimized for charge balance in the off-state, and will typically be more lightly doped than body regions 8. In the on-state, VDMOS 2′ conducts source-drain current Ids in the same manner as described above for non-superjunction VDMOS 2, in this case with current conducted through the n-type drift regions presented by the portions of n-type epitaxial layer 6′ between p-type pillars 9. In the off-state, however, p-type pillars 9 and the n-type drift regions of epitaxial layer 6′ will essentially fully deplete under the typical high drain-to-source voltage, in which case the additional p-type material of pillars 9 extending deep into the structure causes a corresponding amount of charge to also deplete from n-type epitaxial layer 6′, in order to attain charge balance. This additional charge cancellation in the off-state resulting from pillars 9 according to this superjunction construction enables epitaxial layer 6′ to have a higher dopant concentration, and thus a lower on-state resistance Repi, without adversely affecting the breakdown voltage in the off-state.
The gate electrodes in the conventional VDMOS devices of FIGS. 1a and 1b are planar structures, disposed near the surface of the semiconductor and overlying the gate dielectric layer. In contrast, some conventional superjunction and non-superjunction VDMOS devices are constructed with trench gate electrodes. As known in the art, the gate electrode of a trench gate device is disposed within a trench etched into the surface of the device, in a manner that is insulated from the surrounding semiconductor by a gate dielectric. The channel region of the trench gate VDMOS device is oriented vertically, which vertically orients the source-drain current through that channel region.
FIG. 2a illustrates, in cross-section, the physical structure of the bias connection to the source and body regions of conventional VDMOS device 2′ of FIG. 1b for the planar gate electrode case. Non-superjunction devices, such as VDMOS device 2 of FIG. 1a, typically have a similar bias connection structure. In the example of FIG. 2, the bias connection to n+ source regions 10 and body region 8 is made by source metal 14, which is realized as a single metal level metal conductor overlying insulator layer 13 above gate electrodes 12. As known in the art, a sidewall insulator may be present along the edges of gate electrodes 12. Contact openings are etched through insulator layer 13, at which source metal 14 contacts source regions 10 and body regions 8.
As conventional in the art for vertical power integrated circuits, multiple transistor structures of VDMOS device 2′ are connected in parallel, with substrate 4 serving as the drain for all of the transistor structures, and with source metal 14 connecting body regions 8 and source regions 10 for all of the structures in parallel. In a top-down (i.e., plan) view, source metal 14 may thus appear as a single continuous sheet over the active area of VDMOS device 2′. The large source/drain current conducted by VDMOS device 2′ requires the thickness Tmet of source metal 14 to be significantly thicker than metal conductors in low-voltage analog and logic integrated circuits. For example, a source metal thickness on the order of several microns (e.g., 2 to 10 μm) is common in modern vertical power devices.
In the conventional source-gate architecture of FIG. 2a, source regions 10 are implanted in a self-aligned fashion relative to gate electrode 12 as mentioned above. Accordingly, in order to make contact between source metal 14 and p-type body regions 8 in this conventional construction, the contact openings through insulator 13 are overetched into the underlying epitaxial silicon, with that etch extending to a depth Dct fully through source regions 10 and into the underlying body regions 8, as shown in FIG. 2a. Because of this etch into the single-crystal silicon, the deposited source metal 14 will be physically in contact with source regions 10 and also with body region 8.
This conventional source-gate architecture presents limitations to the performance and scalability of the vertical power device. One such limitation is the parasitic gate-to-source capacitance presented between gate electrodes 12 and source metal 14. As known in the art, gate-to-source capacitance in an MOS transistor can limit the switching speed of the device, and as such should be minimized to the extent practicable. Referring to the detail view of VDMOS 2′ shown in FIG. 2b, parasitic gate-to-source capacitance Cgs is presented at both the top surface and side edges of gate electrode 12.
The gate-to-source capacitance Cgs of VDMOS 2′ varies inversely with the thickness Tinsul of insulator layer 13 between the top surface of gate electrode 12 and overlying source metal 14. To maximizing switching performance, therefore, it is desirable to increase this thickness Tinsul as much as possible. However, referring back to the view of FIG. 2a, increases in the thickness Tinsul of insulator layer 13 adversely affects the ability of the deposited source metal 14 to make reliable contact to source regions 10 and body regions 8 for a given contact width Wct. This difficulty is exacerbated by the increased source metal thickness Tmet required by the large source-drain currents of VDMOS 2′. More specifically, as known in the art, the deposition of source metal 14 into a contact opening of a width (i.e., contact width Wct) that is less than twice the thickness Tmet of the deposited film for a given thickness Tinsul of insulator layer 13 can cause self-shadowing or even “bread-loafing” of the deposited metal, in which the deposited thickness of source metal 14 is thinned as it descends into the contact opening. Step coverage of source metal 14 within the contact is thus reduced, rendering VDMOS device 2′ vulnerable to electromigration of source metal 14 during its operating life, thereby increasing device failures and reducing the device reliability. As a result, the extent to which gate-to-source capacitance can be reduced by increasing the insulator thickness Tinsul, for a given contact width Wct, is limited in these conventional gate-source architectures.
Conversely, this interaction between metal thickness Tmet and insulator thickness Tinsul also limits the ability to scale power devices to smaller geometries. The pitch of source and gate structures at the surface of the integrated circuit depends not only on gate width but also on the contact width Wct. But because shrinking of the contact width Wct necessitates reducing either or both of the insulator thickness Tinsul and the source metal thickness Tmet, scaling of the vertical power device structure necessarily comes at a cost of increased parasitic gate-to-source capacitance Cgs or decreased current capability.